中文简介:
2006年毕业于重庆市第八中学,同年进入天津大学,2010年获得电子科学与技术专业学士学位并进入中国科学院半导体研究所开始硕博阶段学习,2015年7月毕业并获得微电子与固体电子学博士学位,目前我在University of Calgary进行博士后工作。

联系邮箱:yangjie(at)semi.ac.cn


—Here is my CV in English

Biography

I was born in Chongqing, China, in December 1987. I received the B.S. degree in electronic science and technology from Tianjian University in 2010, the Ph.D. degree from Institute of Semiconductors, Chinese Academy of Sciences in 2015. I am currently a Postdoctoral Fellow at University of Calgary, Canada.

Education

  • Chinese Academy of Sciences, Beijing, P. R. China
    Ph.D. Microelectronics, July 2015
  • Tianjin University, Tianjin, P. R. China
    B.S. Electronics Science and Technology, 2010 (GPA: Top 10%)
    Graduated with honor, 2010
    First degree scholarship of Tianjin University, 2007-2009

Research Interests

  • VLSI architecture exploration of computer vision and machine learning
  • Parallelization of image processing and machine learning algorithms
  • Deep learning and convolutional neural network

Publication

  • High speed Visual Tracking with Mixed Rotation Invariant Description, Y. Yang, J. Yang, et.al, Electronics Letters.
  • High-speed Target Tracking System Based on a Hierarchical Parallel Vision Processor and Gray-Level LBP Algorithm, Y. Yang, J. Yang, Z. Chen, et.al, IEEE Trans. Systems, Man, and Cybernetics: Systems.
  • High speed vision processor with reconfigurable processing element array based on full-custom distributed memory, Z. Chen, J. Yang, C. Shi, et.al, Japanese Journal of Applied Phyiscs
  • High-speed object detection based on a hierarchical parallel vision chip, Z. Zhang, J. Yang, H. Li, et.al, IEEE International Conference on ASIC, 2015
  • A Novel Vision Chip Architecture for Image Recognition Based on Convolutional Neural Net-work, H. Li, Z. Zhang, and J. Yang, et.al, IEEE International Conference on ASIC, 2015
  • An 860-GHz Terahertz Image Sensor Integrated with Readout Circuit in 180-nm CMOS Process, Z. Liu, L. Liu, and J. Yang, et.al, IEEE Asian Solid-State Circuits Conference
  • A High-speed Vision Processor for Chip Package Visual Inspection, B. Li, J. Yang, Y. Yang, et.al, IEEE International Conference on Solid-State and Integrated circuit Technology, 2014
  • Pixel-parallel Feature Detection on Vision Chip, J. Yang, C. Shi, L. Liu, et.al, Electronics Letters, 50(24), page 1839-1841, 2014
  • A 1000 fps Vision Chip Based on a Dynamically Reconfigurable Hybrid Architecture Comprising a PE Array Processor and Self-Organizing Map Neural Network, C. Shi, J. Yang, Y. Han, et.al., IEEE J. Solid-State Circuits, 49(9), page 2067-2082, 2014
  • A 1000 fps Vision Chip Based on a Dynamically Reconfigurable Hybrid Architecture Compris-ing a PE Array and Self-organizing Map Neural Network, C. Shi, J. Yang, Y. Han, et.al., IEEE ISSCC Dig. Tech. Papers, page 128-129, 2014
  • A Massively Parallel Keypoint Detection and Description (MP-KDD) Algorithm for High-speed Vision Chip, C. Shi, J. Yang, L. Liu, et.al., Science China Information Sciences, 57(10), page 1- 12, 2014
  • A Compact PE Memory for Vision Chips, Cong. Shi, Z. Chen, J. Yang, et.al., Journal of Semi-conductors, 35(9), 2014.
  • A High Speed Multi-level-parallel Array Processor for Vision Chips, C. Shi, J. Yang, N. Wu, et.al., Scince China Information Sciences, 57(6), page 1-12, 2014
  • Heterogeneous Vision Chip and LBP-based Algorithm for High-speed Tracking, J. Yang, C. Shi, L. Liu and N. Wu, Electronics Letters, 50(6), page 438-439, 2014
  • Smart Image Sensing System, J. Yang, C. Shi, Z. Cao, et.al, IEEE Sensors Conference, 2013
  • A Novel Architecture of Local Memory for Programmable SIMD Vision Chip, Z. Chen, J. Yang, C. Shi, et.al., IEEE International Conference on ASIC, 2013

Publications under preparation or under review

  • A Heterogeneous Parallel Vision Chip Processor for High-speed Vision, J. Yang, Y. Yang, et.al(sub)
  • HALO: A Heterogeneous Parallel Processor for Real-time Vision Application, J. Yang, H. Li, L. Liu, et.al
  • My publications are also avaiable @Google Scholar and @Research Gate

Skills

  • Verilog, SystemVerilog
  • VCS, DC, Encounter
  • FPGA design
  • C#, C, Matlab, Python

Contacts

  • Email: yangjie(at)semi.ac.cn or jie.yang2(at)ucalgary.ca